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Thread: Qsys error:While creating NEW IP

  1. #1
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    Jan 2018
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    Red face Qsys error:While creating NEW IP

    Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me

    Verilog code
    Code:
     module coun    (
     LED     ,  // Output of the counter
     clk     ,  // clock Input
     );
     input clk;
     output reg LED;
     reg [31:0] out=0;   
    always @(posedge clk) begin
     out <= out + 1;
     LED=out[29];
    end
    endmodule
    I need step-step training please
    Attached Images Attached Images

  2. #2
    Join Date
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    Default Re: Qsys error:While creating NEW IP

    Hi,

    Image is not clear can you reattach the screen short of the error and interconnect in two image?

    Regards
    Anand

  3. #3
    Join Date
    May 2013
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    Default Re: Qsys error:While creating NEW IP

    Did you check out the training I highlighted here: https://alteraforum.com/forum/showth...ht=#post236429

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