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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

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  1. Post Encryptd altera library mapped Empty

    Started by shyamk, Yesterday 11:56 PM
    • Replies: 0
    • Views: 33
    Yesterday, 11:56 PM Go to last post
    • Replies: 0
    • Views: 98
    June 16th, 2018, 05:48 PM Go to last post
  2. Simulating Cyclone V altera_hps with ModelSim

    Started by eugenek, June 15th, 2018 02:42 AM
    • Replies: 1
    • Views: 120
    June 16th, 2018, 02:42 PM Go to last post
  3. Quartus Editing Features - Find in Files & Find by Reference

    Started by erim, June 15th, 2018 02:14 PM
    • Replies: 1
    • Views: 131
    June 15th, 2018, 10:36 PM Go to last post
    • Replies: 2
    • Views: 136
    June 15th, 2018, 01:51 PM Go to last post
  4. Exclamation Win10 crashes with USB Blaster - any patch available?

    Started by ELI_DVTEK, June 15th, 2018 09:09 AM
    blaster;crash;windows
    • Replies: 0
    • Views: 81
    June 15th, 2018, 09:09 AM Go to last post
  5. SDC File rules for Synchronizers

    Started by aghoras, June 14th, 2018 04:18 PM
    synchronizer timing
    • Replies: 8
    • Views: 213
    June 15th, 2018, 07:09 AM Go to last post
  6. Question Cyclone 10 LP sof2flash unrecognized device family

    Started by bischoef, March 7th, 2018 05:20 AM
    • Replies: 2
    • Views: 596
    June 15th, 2018, 06:10 AM Go to last post
  7. Question SignalTap problem with SoCFPGA configured by HPS

    Started by settem, June 15th, 2018 02:52 AM
    bug, rbf, signaltapii, soc-fpga, u-boot
    • Replies: 2
    • Views: 113
    June 15th, 2018, 04:34 AM Go to last post
  8. Serdes fitter placement ERROR in Quartus II 17.1

    Started by lx@asmpt, June 15th, 2018 12:55 AM
    quartus 17.1, serdes placement error
    • Replies: 0
    • Views: 109
    June 15th, 2018, 12:55 AM Go to last post
  9. Source Synchronous Interface Input and Output Delays

    Started by grsharath, June 13th, 2018 01:26 PM
    • Replies: 1
    • Views: 160
    June 14th, 2018, 01:26 PM Go to last post
  10. Problems trying to configure three FPGAS using the EPC16

    Started by afsaez, June 14th, 2018 08:13 AM
    • Replies: 0
    • Views: 121
    June 14th, 2018, 08:13 AM Go to last post
  11. How do I use N25Q512 Quad-SPI Flash, instead of ECPQ512?

    Started by NicholasLee, January 8th, 2016 02:43 PM
    3 Pages
    1 2 3
    • Replies: 29
    • Views: 14,928
    June 13th, 2018, 11:54 PM Go to last post
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    • Views: 106
    June 13th, 2018, 07:01 PM Go to last post
    • Replies: 0
    • Views: 129
    June 13th, 2018, 11:20 AM Go to last post
  12. Exclamation Quartus Prime 16.1: Cannot Edit PCIe BAR widths!!

    Started by ajmills, February 11th, 2017 04:47 AM
    • Replies: 2
    • Views: 1,302
    June 13th, 2018, 10:09 AM Go to last post
    • Replies: 1
    • Views: 182
    June 13th, 2018, 03:31 AM Go to last post
  13. Compile error whilel using Quartus Prime

    Started by savitha muthanna, May 15th, 2018 06:49 AM
    • Replies: 7
    • Views: 566
    June 13th, 2018, 02:49 AM Go to last post
  14. modelsim does not generate clock signal

    Started by ivushka, June 5th, 2018 10:40 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 652
    June 13th, 2018, 01:33 AM Go to last post
  15. TimeQuest: constraining inout ports

    Started by mfro, June 11th, 2018 07:35 AM
    • Replies: 1
    • Views: 176
    June 12th, 2018, 09:27 PM Go to last post
    • Replies: 4
    • Views: 259
    June 12th, 2018, 02:13 PM Go to last post
  16. Using relative include path with NativeLink?

    Started by fhw72, January 8th, 2018 06:28 AM
    • Replies: 1
    • Views: 522
    June 12th, 2018, 04:38 AM Go to last post
    • Replies: 2
    • Views: 1,751
    June 11th, 2018, 07:21 AM Go to last post
    • Replies: 4
    • Views: 363
    June 11th, 2018, 03:52 AM Go to last post
    • Replies: 2
    • Views: 281
    June 10th, 2018, 12:45 PM Go to last post
  17. Can't (properly) install Prime Lite 17.1.0.590

    Started by jcw, November 27th, 2017 11:04 AM
    • Replies: 4
    • Views: 2,450
    June 10th, 2018, 12:18 PM Go to last post
  18. Cannot edit the generated PLL Intel FPGA IP v18.0

    Started by zeahr, June 4th, 2018 08:49 PM
    • Replies: 2
    • Views: 350
    June 9th, 2018, 08:43 PM Go to last post
    • Replies: 8
    • Views: 1,257
    June 8th, 2018, 10:34 PM Go to last post
  19. Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

    Started by frank2215, May 21st, 2018 10:38 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 783
    June 8th, 2018, 11:59 AM Go to last post

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