Page 1 of 206 1231151101 ... LastLast
Threads 1 to 30 of 6151

Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Interface SD Card through GPIO on DE0-Nano

    Started by macoskey, June 15th, 2018 12:24 PM
    cyclone iv, de0-nano, raspberry pi, sd card
    • Replies: 2
    • Views: 139
    Today, 03:50 AM Go to last post
  2. nStatus held low Cyclone IV EP4CE6E22

    Started by Labo_elec, Today 12:24 AM
    cyclone iv ' nstatus low
    • Replies: 0
    • Views: 31
    Today, 12:24 AM Go to last post
    • Replies: 5
    • Views: 210
    Yesterday, 11:12 PM Go to last post
  3. max10 - external reset

    Started by Mux, Yesterday 09:39 PM
    max10 reset
    • Replies: 0
    • Views: 41
    Yesterday, 09:39 PM Go to last post
  4. Implementing a Large RAM on Cyclone II - is it possible?

    Started by dan11, June 16th, 2018 01:07 PM
    cyclone ii; ram
    • Replies: 4
    • Views: 158
    Yesterday, 02:03 PM Go to last post
  5. Cyclone IV FPGA (EP4CE10E22) circuit

    Started by clros, Yesterday 05:17 AM
    • Replies: 0
    • Views: 119
    Yesterday, 05:17 AM Go to last post
  6. Cyclone IV EP4CE10E22 circuit examples

    Started by clros, Yesterday 04:55 AM
    • Replies: 0
    • Views: 89
    Yesterday, 04:55 AM Go to last post
  7. Max10 Jtag pins as Differential I/O.

    Started by Kozha, June 10th, 2018 12:36 AM
    • Replies: 4
    • Views: 331
    Yesterday, 04:46 AM Go to last post
  8. 5AGXFB3H4F35C5NES device support

    Started by PonyoWoo, June 15th, 2018 08:53 AM
    arria v, arria v gx, arria v gx starter kit, device support
    • Replies: 1
    • Views: 133
    June 16th, 2018, 06:09 PM Go to last post
  9. Spectrum analyzer

    Started by espanyola, June 16th, 2018 05:42 AM
    • Replies: 0
    • Views: 99
    June 16th, 2018, 05:42 AM Go to last post
    • Replies: 1
    • Views: 160
    June 15th, 2018, 06:44 AM Go to last post
  10. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 3
    • Views: 1,617
    June 14th, 2018, 07:14 AM Go to last post
  11. MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

    Started by Vadim_GMI, June 14th, 2018 12:41 AM
    i/o, max10, pll, voltage level
    • Replies: 2
    • Views: 154
    June 14th, 2018, 03:27 AM Go to last post
  12. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    • Replies: 9
    • Views: 339
    June 13th, 2018, 10:30 PM Go to last post
  13. Can I configure Cyclone V GT from Parallel Flash?

    Started by shy@navatek.com, June 13th, 2018 08:46 PM
    • Replies: 0
    • Views: 119
    June 13th, 2018, 08:46 PM Go to last post
  14. Data Transfer from FPGA-to-HPS

    Started by andrew44, June 12th, 2018 11:54 AM
    cyclonev, de0-nano-soc
    • Replies: 6
    • Views: 356
    June 13th, 2018, 01:21 PM Go to last post
  15. Timing failure on internal paths

    Started by mohsinele83, June 8th, 2018 03:12 AM
    • Replies: 4
    • Views: 304
    June 13th, 2018, 03:01 AM Go to last post
  16. Strange PLL Clock causing me failing paths in cyc V design

    Started by Hendrik2k1, June 4th, 2018 04:32 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 689
    June 13th, 2018, 02:46 AM Go to last post
    • Replies: 0
    • Views: 134
    June 13th, 2018, 02:04 AM Go to last post
  17. CYCLONE10GX SERDES clock

    Started by lichjr, June 13th, 2018 12:40 AM
    cyclone10gx, serdes
    • Replies: 0
    • Views: 131
    June 13th, 2018, 12:40 AM Go to last post
  18. Fpga alarm clock (urgent help)!

    Started by emrekayar, June 12th, 2018 06:59 AM
    • Replies: 1
    • Views: 131
    June 12th, 2018, 11:31 PM Go to last post
  19. Exclamation Help me my board doesn't work

    Started by daffenen, June 10th, 2018 04:03 AM
    • Replies: 6
    • Views: 324
    June 11th, 2018, 10:28 PM Go to last post
  20. Max10 PLL input clock switchover example?

    Started by bienle, June 11th, 2018 09:56 PM
    • Replies: 0
    • Views: 168
    June 11th, 2018, 09:56 PM Go to last post
  21. DE2-115 board with DCC AD/DA daughter card

    Started by FMZ, June 10th, 2018 01:51 PM
    ad/da card, de2-115
    • Replies: 2
    • Views: 228
    June 11th, 2018, 09:37 PM Go to last post
    • Replies: 4
    • Views: 268
    June 11th, 2018, 08:04 PM Go to last post
    • Replies: 2
    • Views: 211
    June 11th, 2018, 06:30 PM Go to last post
    • Replies: 2
    • Views: 234
    June 11th, 2018, 11:52 AM Go to last post
  22. Least painless way to get data in & out of FPGA

    Started by eugenek, June 10th, 2018 12:41 PM
    • Replies: 2
    • Views: 236
    June 11th, 2018, 12:48 AM Go to last post
  23. Post FPGA MAX 10: JTAG secure mode

    Started by jayr, June 7th, 2018 09:27 AM
    encryption, fpga, jtag secure mode, max10
    • Replies: 3
    • Views: 272
    June 10th, 2018, 08:25 PM Go to last post

Thread Display Options

Use this control to limit the display of threads to those newer than the specified time frame.

Allows you to choose the data by which the thread list will be sorted.

Order threads in...

Note: when sorting by date, 'descending order' will show the newest results first.

Icon Legend

Contains unread posts
Contains unread posts
Contains no unread posts
Contains no unread posts
More than 15 replies or 150 views
Hot thread with unread posts
More than 15 replies or 150 views
Hot thread with no unread posts
Closed Thread
Thread is closed
Thread Contains a Message Written By You
You have posted in this thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •